The example design makes use of one or two AXI Traffic Generators based upon the AXI protocol selected in Vivado IDE.
• The ATG is used in the example design to write the raw data of the packet to the AXI Ethernetlite IP core and also to read/write the control/status registers of the core. The ATG determines the test pass/fail condition based upon the status read from core.
• One ATG is used in system test mode to control the transaction sequence in all configurations.
• The other ATG is used in AXI4 mode and is only instantiated when the AXI protocol selected is AXI4 for the AXI Ethernetlite core.
The ATG takes four COE files as input and provides Done and Status pins as outputs which determine the result of the tests.