AXI4-Lite Protocol without Internal Loopback - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

Document ID
PG135
Release Date
2021-11-02
Version
3.0 English

When the AXI4-Lite protocol is selected without Internal Loopback:

The ATG in system test mode with two AXI channels enabled is used to write a Destination Address, Source Address, and test data into the 2k Memory present in core.

The example design programs the registers in the AXI Ethernetlite core to indicate the number of bytes in a packet and to state that data is ready for packet transmission.

The AXI Ethernetlite IP core generates the Ethernet packet and transmits it through the MII interface.

Another instance of the AXI Ethernetlite IP core that is used in the example design receivse the Ethernet packet.

A CRC check that is performed by default in the IP assures the correct reception of the packet and updates the status register to indicate the same.

The second channel of the ATG is connected to the partner AXI Ethernetlite IP core which reads the status register and gives a test pass/fail condition through the ATG Status and Done pins

Figure 5-1: AXI4-Lite Example Design without Internal Loopback

X-Ref Target - Figure 5-1

axi4-lite.jpg

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