When Internal Loopback option is selected with Loopback:
• When the internal loopback option is enabled in either AXI4-Lite or AXI4 operating mode, the example design does not generate the partner IP because the single instance of the AXI Ethernetlite core performs transmit and receive operations.
• The ATG configures the IP memory with raw data and starts the packet transmission by updating the TX registers. The packet transmitted is looped back internally to the receiver circuitry. The MII interface extends to the test bench and is open at that hierarchy.
• The receiver takes in the packet and updates the status registers based upon the CRC check results.
• The ATG reads the receiver status registers to determine the test pass/fail condition.
X-Ref Target - Figure 5-3
X-Ref Target - Figure 5-4