When the AXI4 protocol is selected without Internal Loopback:
• Two ATGs are used: one in AXI4 mode is connected to the AXI Ethernetlite IP core and the other ATG in system test mode is used to configure the ATG Full mode.
• The ATG in system test mode configures another ATG to generate a burst transaction to transfer data into the AXI Ethernetlite IP core TX buffer. The content to be transferred in the AXI burst transaction is also loaded into ATF FULL using the system test mode.
• The ATG then updates the register in the AXI Ethernetlite core to start transmission of Ethernet packets.
• Another instance of the AXI Ethernetlite core that is used in the example design receives the Ethernet packet and updates the status registers based upon the CRC check performed.
• Another instance of ATG FULL connected to the partner IP reads the status and passes it to the ATG in system test mode which determines the test pass/fail condition.
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X-Ref Target - Figure 5-2 
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