The AXI Ethernetlite example design makes use of the clocking wizard to supply clocks and resets to all other blocks in the design.
The clocking wizard is configured to provide two clocks.
• The first output with the frequency value with the option given in Vivado IDE; this is supplied as the primary clock to all blocks in the example design.
• The second output with the frequency 25 MHz which is the input for phy_tx_clk and phy_rx_clk for the AXI Ethernetlite IP core. The locked signal from the wizard is appropriately used as a reset.