Customizing and Generating the Core - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

This section includes information about using Xilinx tools to customize and generate the core in the Vivado® Design Suite.

If you are customizing and generating the core in the IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 4] for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value you can run the validate_bd_design command in the Tcl Console.

To access the AXI Ethernet Lite, perform the following:

1. Open a project by selecting File > Open Project or create a new project by selecting File > New Project .

2. Open Vivado IP Catalog and choose Embedded Processing/High Speed Peripheral.

3. Double-click AXI Ethernet Lite to display the AXI Ethernet Lite Vivado IDE.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 1] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 5] .

Note: Figure in this chapter is an illustration of the Vivado IDE. This layout might vary from the current version.

Figure 4-1: Vivado IDE

X-Ref Target - Figure 4-1