• Parameterized AXI4 slave interface based on the AXI4 or AXI4-Lite specification for transmit and receive data dual port memory access
• Media Independent Interface (MII) for connection to external 10/100 Mb/s PHY transceivers
• Independent internal 2K byte TX and RX dual port memory for holding data for one packet
• Optional dual buffer memories, 4K byte ping-pong, for TX and RX
• Receive and Transmit Interrupts
• Optional Management Data Input/Output (MDIO) interface for PHY access
• Internal loopback support
• Accepts messages addressed to its unicast address and the broadcast address.