Global Interrupt Enable Register (GIE) - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

Document ID
PG135
Release Date
2021-11-02
Version
3.0 English

The Global Interrupt Enable register is a 32-bit read/write register ( This Figure ). The Global Interrupt Enable Register provides the master enable/disable for the interrupt output (IP2Intc_Irpt signal) to the processor. The bit definition of this register is shown in Table: Global Interrupt Enable Register (0x07F8) .

Figure 2-7: Global Interrupt Enable

X-Ref Target - Figure 2-7

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Table 2-9: Global Interrupt Enable Register (0x07F8)

Bits

Name

Access

Reset value

Description

31

GIE

Read/Write

0

Global Interrupt Enable bit

30:0

Reserved

N/A

N/A

Reserved