The AXI Ethernet Lite MAC I/O signals are listed and described in Table: I/O Signal Descriptions .
Signal Name |
Interface |
I/O |
Initial
|
Description |
---|---|---|---|---|
System Signals |
||||
s_axi_aclk |
System |
I |
- |
AXI4 clock (Processor clock domain) |
s_axi_aresetn |
System |
I |
- |
AXI4 reset, active-Low |
ip2intc_irpt |
System |
O |
0 |
Edge rising interrupt |
AXI4 Write Address Channel Signals |
||||
s_axi* |
S_AXI |
- |
- |
See Appendix A of the Vivado AXI Reference Guide (UG1037) [Ref 2] for the description of AXI4 Signals. |
AXI Ethernet Lite MAC Interface Signals |
||||
phy_tx_clk |
PHY |
I |
- |
Ethernet transmit clock input from PHY |
phy_rx_clk |
PHY |
I |
- |
Ethernet receive clock input from PHY |
phy_rx_data[3:0] |
PHY |
I |
- |
Ethernet receive data. Input from Ethernet PHY. |
phy_tx_data[3:0] |
PHY |
O |
0 |
Ethernet transmit data. Output to Ethernet PHY. |
phy_dv |
PHY |
I |
- |
Ethernet receive data valid. Input from Ethernet PHY. |
phy_rx_er |
PHY |
I |
- |
Ethernet receive error. Input from Ethernet PHY. |
phy_tx_en |
PHY |
O |
0 |
Ethernet transmit enable. Output to Ethernet PHY. |
phy_crs |
PHY |
I |
- |
Ethernet carrier sense input from Ethernet PHY |
phy_col |
PHY |
I |
- |
Ethernet collision input from Ethernet PHY |
phy_rst_n |
PHY |
O |
- |
PHY reset, active-Low |
PHY |
O |
0 |
Ethernet to PHY MII Management clock |
|
PHY |
I |
- |
PHY MDIO data input from 3-state buffer |
|
PHY |
O |
0 |
PHY MDIO data output to 3-state buffer |
|
PHY |
O |
0 |
PHY MDIO data output enable to 3-state buffer |
|
Notes: 1. This port is unused when Enable MII Management Module is disabled in the Vivado IDE. Output has default assignment. 2. The signal phy_mdio is a bidirectional port. The insertion of the 3-state buffer is automatically done by the Vivado IP integrator tool. You do not need to connect phy_mdio_i , phy_mdio_o and phy_mdio_t signals manually when using IP in IP integrator. |