The AXI Ethernet Lite MAC core can be configured in internal loopback mode by setting the parameter Enable Internal Loopback is checked in the Vivado IDE and by setting bit 4 of the Transmit Control Register (Ping). In loopback mode, the logic uses BUFG for PHY clock switching. In this mode, the AXI Ethernet Lite MAC core routes back data on the TX lines to the RX lines. The loopback mode can be tested only in full duplex mode. In this mode, the core does not accept any data from the PHY and phy_tx_clk and phy_tx_en are used as phy_rx_clk and phy_dv internally ( This Figure ).