The MDIOCTRL is a 32-bit read/write register (
This Figure
). This register contains status and control information of the MDIO interface. The MDIO Enable (bit 3) of this register is used to enable the MDIO interface. The bit definition of this register is shown in
Table: MDIO Control Register (0x07F0)
.
Figure 2-15:
MDIO Control Register
|
X-Ref Target - Figure 2-15
|
Table 2-17:
MDIO Control Register (0x07F0)
|
Bits
|
Name
|
Access
|
Reset Value
|
Description
|
|
31:4
|
Reserved
|
N/A
|
N/A
|
Reserved
|
|
3
|
MDIO Enable
|
Read/Write
|
0
|
MDIO enable bit
0 – Disable MDIO interface
1 – Enable MDIO interface
|
|
2:1
|
Reserved
|
N/A
|
N/A
|
Reserved
|
|
0
|
Status
|
Read/Write
|
0
|
MDIO status bit
0 – MDIO transfer is complete and core is ready to accept a new MDIO request
1 – MDIO transfer is in progress. Setting this bit initiates an MDIO transaction. When the MDIO transaction is complete, the
AXI Ethernet Lite MAC
core clears this bit.
|
