The Management Data Input/Output Master Interface is included in the design if the parameter Enable MII Management Module is checked in the Vivado® Integrated Design Environment (IDE). Including this logic allows AXI Ethernet Lite MAC core to access PHY configuration registers. The MDIO Master Interface module is designed to incorporate the features described in IEEE 802.3 Media Independent Interface (MII) specification.
The MDIO module generates management data clock to the PHY ( phy_mdc ) with a minimum period of 400 ns. The signal phy_mdc is sourced to PHY as timing reference for transfer of information on the phy_mdio (Management Data Input/Output) data signal.
The phy_mdio signal is a bidirectional signal between the PHY and MDIO module. It is used to transfer control and status information between the PHY and the MDIO module. The control information is driven by the MDIO module synchronously with respect to phy_mdc and is sampled synchronously by the PHY. The status information is driven by the PHY synchronously with respect to phy_mdc and is sampled synchronously by the MDIO module. The signal phy_mdio is driven through a 3-state circuit that enables either the MDIO module or the PHY to drive the circuit.
The MDIO interface uses a standard method to access PHY management registers. The MDIO module supports up to 32 PHY devices. To access each PHY device, the PHY device address must be written into the MDIO Address (MDIOADDR) register followed by PHY register address ( This Figure ). This module supports access to up to 32 PHY management registers. The write transaction data for the PHY must be written into MDIO Write Data (MDIOWR) register and the status data from the PHY register can be read from the MDIO Read Data (MDIORD) register. The MDIO Control (MDIOCTRL) register is used to initiate to management transaction on the MDIO lines.
The AXI Ethernet Lite MAC requires that the PHY device address and PHY register address be stored in the MDIO Address Register at address 0x07E4 before the software sets the status bit in the MDIO Control Register at offset 0x07F0 .
The software sequence for initiating a PHY register write transaction is:
1. The software reads the MDIOCTRL register to verify if the MDIO master is busy executing a previous request. If the status bit is 0, the MDIO master can accept a new request.
2. The software stores the PHY device address and PHY register address and writes 0 to Bit[10] in the MDIOADDR register at address 0x07E4 .
3. The software stores the PHY register write data in the MDIOWR register at address 0x07E8 .
4. The software writes 1 in the MDIO enable bit in the MDIOCTRL register at address 0x07F0 .
5. The software writes a 1 to the status bit at address 0x07F0 (Bit[0] on the data bus) to start the MDIO transaction.
6. After completing the MDIO write transaction, the AXI Ethernet Lite MAC core clears the status bit.
7. The software monitors the status bit and waits until it is set to 0 by the AXI Ethernet Lite MAC before initiating new transaction on the MDIO lines.
The software sequence for initiating a PHY register read transaction is:
1. The software reads the MDIOCTRL register to verify if the MDIO master is busy executing a previous request. If the status bit is 0, the MDIO master can accept a new request.
2. The software stores the PHY device address and PHY register address and writes 1 to bit 10 in the MDIOADDR register at address 0x07E4 .
3. The software writes 1 in the MDIO enable bit in the MDIOCTRL register at address 0x07F0 .
4. The software writes a 1 to the status bit at address 0x07F0 (bit 0 on the data bus) to start the MDIO transaction.
5. After completing the MDIO Read transaction, the AXI Ethernet Lite MAC core clears the status bit.
The software monitors the status bit and waits until it is set to 0 by the AXI Ethernet Lite MAC core before initiating a new transaction on the MDIO lines.