Receive Clock - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

The receive clock [ phy_rx_clk ] is also generated by the external PHY but is derived from the incoming Ethernet traffic. Similarly to the transmit clock, the PHY provides one clock cycle for each nibble of data transferred, resulting in a 2.5 MHz clock for 10BASE-T operation and 25 MHz for 100BASE-T operation with a duty cycle of between 35% and 65%, inclusive, while incoming data is valid [ phy_dv is 1].

The minimum high and low times of the receive clock are at least 35% of the nominal period under all conditions. The receive clock is used by the AXI Ethernet Lite MAC core to sample the receive data [ phy_rx_data(3:0) ] and control signals [ phy_dv and phy_rx_er ] from the PHY.