The Receive Control register for the ping buffer is a 32-bit read/write register (
This Figure
). This register indicates whether there is a new packet in the ping buffer. The bit definition of this register is shown in
Table: Receive Control Register (0x17FC)
.
Figure 2-10:
Receive Control Register (Ping)
|
X-Ref Target - Figure 2-10
|
Table 2-12:
Receive Control Register (0x17FC)
|
Bits
|
Name
|
Access
|
Reset value
|
Description
|
|
31:4
|
Reserved
|
N/A
|
N/A
|
Reserved
|
|
3
|
Interrupt Enable
|
Read/Write
|
0
|
Receive Interrupt Enable bit
0 – Disable receive interrupt
1 – Enable receive interrupt
|
|
2:1
|
Reserved
|
N/A
|
N/A
|
Reserved
|
|
0
|
Status
|
Read/Write
|
0
|
Receive status indicator
0 – Receive ping buffer is empty.
AXI Ethernet Lite MAC
can accept new valid packet.
1 – Indicates presence of receive packet ready for software processing. When the software reads the packet from the receive ping buffer, the software must clear this bit.
|
