Receiver - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

This block consists of the RX interface, loopback control MUX, RX FIFO, CRC checker and Receive Control module. Receive data signals from the PHY are passed through the loopback control MUX and stored in the RX FIFO. If loopback is enabled, data on the TX lines is passed to the RX FIFO. The CRC checker module calculates the CRC of the received frame and if the correct CRC is found, receive control logic generates the frame receive interrupt.