The AXI Ethernet Lite core works on the s_axi_aresetn , which is active-Low. The reset assertion timing is dependent upon the slowest AXI Ethernet Lite clock. In general allow thirty clock cycles of the slowest AXI Ethernet Lite clock to elapse before accessing the core. Failure to do causes unpredictable behavior.
The phy_rst_n output signal is an active-Low reset that is tied directly to the AXI reset signal ( s_axi_aresetn ). This signal can be connected to the active-Low reset input of a PHY device.