The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
11/10/2021 |
3.0 |
Added support for Versal® ACAP |
|
07/08/2020 |
3.0 |
Editorial updates only. No technical content updates. |
|
05/22/2019 |
3.0 |
Editorial updates only. No technical content updates. |
|
12/05/2018 |
3.0 |
Added a note on the cover page. |
|
11/18/2015 |
3.0 |
Added support for UltraScale+ families. |
|
10/01/2014 |
3.0 |
• Document updated only for revision change. • Updated Note #3 in Table 2-5: I/O Signal Descriptions. • Added Important Note in Software Sequence for Receive Ping-Pong section. • Added User Parameter table in Design Flow Steps chapter. |
|
04/02/2014 |
3.0 |
• Added example design addition. • Changed MTBF. |
|
12/18/2013 |
2.0 |
• Added UltraScale™ architecture support. • Changed all signal and port names to lowercase. |
|
03/20/2013 |
2.0 |
Initial version of this product guide. This product guide replaces ds787. |