If Number of Receive Buffers is set to 1 then two memory buffers exist for the receive data. The original (ping receive buffer) remains at the same memory location. The second (pong receiver buffer) is mapped to 0x1800 through 0x1FFC . Data is stored the same way in the pong buffer as it is in the ping buffer.
The software sequence for processing a receive packet(s) with Number of Receive Buffers = 1 is:
1. The software monitors the ping receive status bit until it is set to 1 by the AXI Ethernet Lite MAC , or waits for a receive complete interrupt, if enabled.
2. When the ping status is set to 1, or a receive complete interrupt has occurred, the software reads the entire receive data out of the ping dual port memory.
3. The AXI Ethernet Lite MAC receives the next packet and stores it in the pong receive buffer.
4. The software writes a 0 to the ping receive status bit, enabling the AXI Ethernet Lite MAC core to receive another packet in the ping receive buffer.
5. The software monitors the pong receive status bit until it is set to 1 by the AXI Ethernet Lite MAC core, or waits for a receive complete interrupt, if enabled.
6. When the pong status is set to 1, or a receive complete interrupt has occurred, the software reads the entire receive data out of the ping dual port memory.
7. The hardware always writes the first received packet, after a reset, to the ping buffer; the second received packet is written to the pong buffer and the third received packet is written to the ping buffer, and so forth.
IMPORTANT:
Not clearing the status bit of ping and pong buffer results in packet loss.
For example, after correctly receiving two packet status bits of both ping and pong, buffers are set to 1 by the AXI Ethernet Lite MAC. If software only clears status bit of pong buffer, then the third packet would be lost (as this packet is intended to be received by ping buffer but its status bit is not cleared) and the IP would correctly receive the fourth packet.