Software Sequence for Transmit with Ping Buffer - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

The AXI Ethernet Lite MAC core requires that the length of the transmit data to be stored in address 0x07F4 before the software sets the status bit at offset 0x07FC . The software sequence for initiating a transmit is:

The software stores the transmit data in the dual port memory starting at address 0x0

The software writes the length data in the dual port memory at address 0x07F4

The software writes a 1 to the status bit at address 0x07FC (Bit[0] on the data bus)

The software monitors the status bit and waits until it is set to 0 by the AXI Ethernet Lite MAC core before initiating another transmit

If the transmit interrupt and the global interrupt are both enabled, an interrupt occurs when the AXI Ethernet Lite MAC core clears the status bit

The transmit interrupt, if enabled, also occurs with the completion of writing the Ethernet MAC address

Setting the status bit to a 1 initiates the AXI Ethernet Lite MAC core transmit to perform the following functions:

Generates the preamble and start-of-frame fields

Reads the length and the specified amount of data out of the dual port memory according to the length value, adding padding if required

Detects any collision and performs any jamming, backs off and retries, if necessary

Calculates the CRC and appends it to the end of the data

Clears the status bit at the completion of the transmission

Clearing the status bit causes a transmit complete interrupt, if enabled