If Number of Transmit Buffers is set to 1, two memory buffers exist for the transmit data. The original (ping transmit buffer) remains at the same memory address and controls the global interrupt enable. The second (pong buffer) is mapped at 0x0800 through 0x0FFC . The length and status must be used in the pong buffer the same as in the ping buffer. The I bit and Global Interrupt Enable (GIE) bit are not used from the pong buffer (that is, the I bit and GIE bit of the ping buffer alone control the I bit and GIE bit settings for both buffers). The Ethernet MAC address can be set from the pong buffer. The transmitter always empties the ping buffer first after a reset. Then, if data is ready to be transmitted from the pong buffer, that transmission takes place. However, if the pong buffer is not ready to transmit data, the AXI Ethernet Lite MAC core begins to monitor both the ping and pong buffers and transmits the buffer that is ready first.
The software sequence for initiating a transmit with both a ping and pong buffer is:
• The software stores the transmit data in the dual port memory starting at address 0x0 .
• The software writes the length data in the dual port memory at address 0x07F4 .
• The software writes a 1 to the status bit at address 0x07FC (Bit[0] on the data bus).
• The software can write to the pong buffer ( 0x0800 – 0x0FFC ) at any time.
• The software monitors the status bit in the ping buffer and waits until it is set to 0, or waits for a transmit complete interrupt, before filling the ping buffer again.
• If the transmit interrupt and the global interrupt are both enabled, an interrupt occurs when the AXI Ethernet Lite MAC core clears the status bit.
• The transmit interrupt, if enabled, also occurs with the completion of writing the Ethernet MAC address.
Setting the status bit to a 1 initiates the AXI Ethernet Lite MAC core transmit which performs the following functions:
• Generates the preamble and start-of-frame fields
• Reads the length and the specified amount of data out of the dual port memory according to the length value, adding padding if required
• Detects any collision and performs any jamming, backs off, and retries if necessary
• Calculates the CRC and appends it to the end of the data
• Clears the status bit at the completion of the transmission
• Clearing the status bit causes a transmit complete interrupt if enabled
• The hardware then transmits the pong buffer if it is available, or begins monitoring both ping and pong buffers until data is available