Test Bench - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

The following file describes the demonstration test bench for the AXI Ethernetlite core.


The demonstration test bench is a simple VHDL program to exercise the example design and the core.

The demonstration test bench performs the following tasks:

Instantiates the example design top

Connects the MII interfaces of DUT and AXI Ethernetlite partner IP core in non-loopback cases

Generates clock and reset inputs for the clocking wizard

Takes Done and Status pins from the ATG and determines the simulation status

Figure 6-1: Test Bench

X-Ref Target - Figure 6-1