The following file describes the demonstration test bench for the AXI Ethernetlite core.
<project_name>/<project_name>.srcs/sources_1/ip/<component_name>/<component_name>example_design/<component_name>_exdes.vhd
The demonstration test bench is a simple VHDL program to exercise the example design and the core.
The demonstration test bench performs the following tasks:
• Instantiates the example design top
• Connects the MII interfaces of DUT and AXI Ethernetlite partner IP core in non-loopback cases
• Generates clock and reset inputs for the clocking wizard
• Takes Done and Status pins from the ATG and determines the simulation status
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X-Ref Target - Figure 6-1 
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