The transmit clock [ phy_tx_clk ] is generated by the external PHY and must be used by the AXI Ethernet Lite MAC core to provide transmit data [ phy_tx_data [3:0] ] and to control signals [ phy_tx_en ] to the PHY.
The PHY provides one clock cycle for each nibble of data transferred resulting in a 2.5 MHz clock for 10BASE-T operation and 25 MHz for 100BASE-T operation at ± 100 ppm with a duty cycle of between 35% and 65%, inclusive. The PHY derives this clock from an external oscillator or crystal.