Transmit Interface - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

The transmit data should be stored in the dual port memory starting at address 0x0 . Because of the word aligned addressing, the second four bytes are located at 0x4 . The 32-bit interface requires that all four bytes be written at once; there are no individual byte enables within one 32-bit word. The transmit data must include the destination address (6 bytes), the source address (6 bytes), the type/length field (2 bytes), and the data field
(0 – 1,500 bytes). The preamble, start-of-frame, and CRC should not be included in the dual port memory. The destination, source, type/length, and data must be packed together in contiguous memory.

Dual port memory addresses 0x07F4 is used to store the length (in bytes) of the transmit data stored in dual port memory. The higher 8 bits of the length value should be stored in data bits 15 to 8, while the lower 8 bits should be stored in data bits 7 to 0.

Dual port memory address 0x07F8 is used to set the global interrupt enable (GIE) bit. Setting the GIE = 0 prevents the IP2INTC_Irpt from going active during an interrupt event. Setting GIE = 1 allows the ip2intc_irpt to go active when an interrupt event occurs.

The least two significant bits of dual port memory address 0x07FC are control bits (Program or "P" and Status or "S"). The fourth bit (Bit[3] on the data bus) (Transmit Interrupt Enable or "I") is used to enable transmit complete interrupt events. This event is a pulse and occurs when the memory is ready to accept new data. The transmit complete interrupt occurs only if GIE and this bit are both set to 1.

Figure 3-2: Transmit Dual Port Memory

X-Ref Target - Figure 3-2