The PHY drives the Receive Data Valid ( phy_dv ) signal to indicate that the PHY is driving recovered and decoded nibbles on the phy_rx_data(3:0) bus and that the data on phy_rx_data(3:0) is synchronous to phy_rx_clk . The signal phy_dv is driven synchronously to phy_rx_clk . The signal phy_dv remains asserted continuously from the first recovered nibble of the frame through the final recovered nibble.
For a received frame to be correctly received by the AXI Ethernet Lite MAC , phy_dv must encompass the frame, starting no later than the Start-of-Frame Delimiter (SFD) and excluding any End-of-Frame delimiter. This Figure shows the behavior of phy_dv during frame reception.
