The PHY drives the Receive Data bus phy_rx_data(3:0) synchronously to phy_rx_clk . The signal phy_rx_data(3:0) contains recovered data for each phy_rx_clk period in which phy_dv is asserted. The signal phy_rx_data(0) is the least significant bit. The AXI Ethernet Lite MAC must not be affected by phy_rx_data(3:0) while phy_dv is deasserted.
The AXI Ethernet Lite MAC should ignore a special condition that occurs while phy_dv is deasserted; the PHY can provide a False Carrier indication by asserting the phy_rx_er signal while driving the value 1110 onto phy_rx_data(3:0) .