phy_tx_data(3:0) - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

The AXI Ethernet Lite MAC drives the Transmit Data bus phy_tx_data(3:0) synchronously to phy_tx_clk . The signal phy_tx_data(0) is the least significant bit. The PHY transmits the value of phy_tx_data on every clock cycle that phy_tx_en is asserted. The order of the bits, nibbles, and bytes for transmit and receive are shown in This Figure .

Figure 2-2: Byte/Nibble Transmit and Receive Order

X-Ref Target - Figure 2-2