<project_name>/<project_name>.srcs/sources_1/ip/ - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

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3.0 English

The <project directory> contains all the Vivado design tool project files.

Table 5-1: project_name>/<project_name>.srcs/sources_1/ip/



Synth/<component name>.v|vhd

Synthesis wrapper generated by the Vivado design tools

Sim/<component name>.v|vhd

Simulation wrapper generated by the Vivado design tools

<component name>.xci

Vivado tools project-specific option file; can be used as an input to the Vivado design tools.

<component name>.vho|veo

VHDL or Verilog instantiation template

<component name>_ooc.xdc

Out of Context constraints for IP

COE Files

These files are intended for the use with the example design. Right-click on the generated IP and select Open Example Design in the Vivado design tools to create the example design project