The <project directory> contains all the Vivado design tool project files.
|
Name |
Description |
|---|---|
|
Synth/<component name>.v|vhd |
Synthesis wrapper generated by the Vivado design tools |
|
Sim/<component name>.v|vhd |
Simulation wrapper generated by the Vivado design tools |
|
<component name>.xci |
Vivado tools project-specific option file; can be used as an input to the Vivado design tools. |
|
<component name>.vho|veo |
VHDL or Verilog instantiation template |
|
<component name>_ooc.xdc |
Out of Context constraints for IP |
|
COE Files |
These files are intended for the use with the example design. Right-click on the generated IP and select Open Example Design in the Vivado design tools to create the example design project |