AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138) - 7.2 English

Document ID: PG138
Release Date: 2022-11-16
Version: 7.2 English

AXI 1G/2.5G Ethernet Subsystem v7.2 Product Guide
IP Facts
Introduction
Features
Overview
Navigating Content By Design Process
How to Use This Document
Feature Summary
Licensing and Ordering Information
Product Specification
Functional Description
Partial TCP/UDP Checksum Offload in Hardware
Full TCP/UDP Checksum Offload in Hardware
Frame Transmission
Padding
FCS Pass Through
Virtual LAN (VLAN) Frames
Maximum Frame Length and Jumbo Frames
Frame Reception
Frame Reception with Errors
FCS Pass Through or Stripping
Virtual LAN (VLAN) Frames
Maximum Frame Length and Jumbo Frames
Length/Type Field Error Checks
Enabled
Disabled
Address Filtering
Basic Mode
Using the Address Filters
Extended Multicast Address Filtering Mode
General
Implementation Details
Flow Control
Transmitting a Pause Control Frame
Receiving a Pause Control Frame
Extended VLAN Support
VLAN General Information
VLAN Translation
Transmit Path
Receive Path
VLAN Tagging and Double Tagging
VLAN Stripping
Order of Extended VLAN Functions When Combined
Using the MII Management to Access Internal or External PHY Registers
Serial Gigabit Media Independent Interface
SGMII Auto-Negotiation
SGMII over LVDS
1000BASE-X PCS/PMA
PCS/PMA
PMD
1000BASE-X Auto-Negotiation
1000BASE-X over LVDS
2.5G Data Rate Support
Generating Subsystem for 2.5G Operation
Standards
Performance
Resource Utilization
Port Descriptions
AXI4-Lite Interface
AXI4-Stream Transmit Interface
AXI4-Stream Receive Interface
Ethernet AVB Transmit Interface
Ethernet AVB Receive Interface
Ethernet AVB Interrupt Interface
Reference RTC Interface
System Interface
Ethernet System Interface
Ethernet MII Interface
Ethernet GMII Interface
Ethernet SGMII and 1000BASE-X Interface
Dynamic Switching Signal Port
Ethernet Transceiver Debug Interface
Ethernet RGMII Interface
IO Delay Calibration Ports for Ethernet RGMII Interface
Ethernet MII Management Interface
IEEE 1588 Transmit Timestamp Ports
IEEE 1588 Received Timestamp Ports
IEEE 1588 System Timer Ports
Flow Control Interface
Priority Flow Control Interface (802.1Qbb)
Statistics Vectors
Transmit Statistics Vector
Receive Statistics Vector
Register Space
.h Header File
Reset and Address Filter Register
Transmit Pause Frame Register
Transmit Inter Frame Gap Adjustment Register
Interrupt Status Register
Interrupt Pending Register
Interrupt Enable Register
Transmit VLAN Tag Register
Receive VLAN Tag Register
Unicast Address Word Lower Register
Unicast Address Word Upper Register
VLAN TPID Word 0 Register
VLAN TPID Word 1 Register
PCS PMA TEMAC Status Register
Statistics Counters
TEMAC Receive Configuration Word 0 Register
TEMAC Receive Configuration Word 1 Register
TEMAC Transmit Configuration Register
TEMAC Flow Control Configuration Register
TEMAC Ethernet MAC Speed Configuration Register
Receive Max Frame Configuration Register
Transmit Max Frame Configuration Register
Transmit Timestamp Adjust Control Register
ID Register
Ability Register
MDIO Setup Register
MDIO Control Register
MDIO Write Data Register
MDIO Read Data Register
Interrupt Status Register
Interrupt Pending Register
Interrupt Enable Register
Interrupt Clear Register
Unicast Address Word 0 Register
Unicast Address Word 1 Register
Frame Filter Control Register
Frame Filter Enable Register
Frame Filter Value Register
Transmit VLAN Data Table
Receive VLAN Data Table
AVB Addressing
Receive PTP Packet Buffer — Offset 0x00010000 – 0x00010FFF
Transmit PTP Packet Buffer — Offset 0x00011000 – 0x000117FF
AVB TX/RX Configuration — Offset 0x00012000 – 0x0001201B
AVB RTC Configuration — Offset 0x00012800 – 0x000128FF
Multicast Address Table — Offset 0x0002_0000-0x0003_FFFF
Enhancements to the 1G/2.5G Ethernet PCS/PMA or Subsystem MDIO Configuration/Status Registers
Gigabit Ethernet PCS/PMA Management Registers
Designing with the Subsystem
Design Guidelines
Customize and Generate the Subsystem
Examine the Generated Design for This Hierarchical Block
Keep It Registered
Recognize Timing Critical Signals
Make Only Allowed Modifications
Clocking
Resets
Design Parameters
Allowable Parameter Combinations
AXI4-Stream Interface
Packetized
Aligned Strobe
Throttling
Dual Channel AXI4-Stream
Functional Description
Transmit AXI4-Stream Interface
Normal Transmit AXI4-Stream Transfer – Flag=0xA
Normal Transmit AXI4-Stream Control Words
Receive Status Transmit AXI4-Stream Transfer – Flag=0x5
Receive AXI4-Stream Interface
Mapping AXI DMA IP Buffer Descriptor Fields to AXI4-Stream Fields
Ethernet Audio Video Bridging
AVB AXI4-Stream Interface
Transmit Interface
Receive Interface
Design Flow Steps
Customizing and Generating the Subsystem
Customizing the Subsystem in the Vivado IDE
Customizing the Subsystem to Share Resources across Multiple Instances
Example 1: Sharing IDELAYCTRL in RGMII Mode among Multiple Subsystem Instances(Applicable for Non-Versal Devices)
Example 2: Sharing GT Quad Base IP in 1000BASE-X Mode among Multiple AXI Ethernet Subsystem Instances (Applicable for Versal ACAP)
Example 3: Sharing GT COMMON in 1000BASE-X Mode among Multiple Subsystem Instances (Applicable for Non-Versal Devices)
Example 4: Sharing Clock and Reset Sequence for Asynchronous 1000BASE-X/SGMII over LVDS Mode among Multiple Subsystem Instances
Using Designer Assistance for the Subsystem
For Versal ACAP Designs
User Parameters
Output Generation
Constraining the Subsystem
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Components of Example Design
10/100/1000 Mb/s Ethernet FIFO
rx_client_fifo
tx_client_fifo
Basic Pattern Generator Module
Address Swap
Pattern Generator
Pattern Checker
AXI4-Lite Control State Machine
Targeting the Example Design to a Board
Board-Specific Configurations
Bring-Up Sequence
KC705 Board
KCU105 Board
VCU118/KCU116 Board
Test Bench
Test Bench Functionality
DEMO Mode
DEMO Mode with Frame Filter
BIST Mode
Changing the Test Bench
DEMO Mode
Changing Frame Data
Changing Frame Error Status
BIST Mode
IEEE 1588 Timestamping
Generating the Subsystem for 1588 Operation
Functional Description
Supported Features
Devices and Physical Interface
IEEE 1588 Supported Features
Architecture Overview
Transmitter
1588 Frame-by-Frame Timestamp Operation
Transmitter Latency and Timestamp Adjustment
Receiver
1588 Frame-by-Frame Timestamp Operation
Receiver Latency and Timestamp Adjustment
Latency Values for the 1588 Enabled Configuration
Latency Values – Simulation
Latency Values – Theoretical
Received Timestamp Ports (Out-of-Band)
Received Frame Timestamp In-line with Frame Reception
Providing the Command Field Out-of-Band
Providing the Command Field In-Line
IEEE 1588 Mode Interfaces
Logic Utilization
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Changes from v7.1 to v7.2
Changes from v7.0 to v7.1
Changes from v5.0 to v6.0
Changes from v4.0 to v5.0
Debugging
Finding Help on Xilinx.com
Documentation
Solution Centers
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Hardware Debug
Interface Debug
AXI4-Lite Interfaces
AXI4-Stream Interfaces
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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