AVB AXI4-Stream Interface - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The AVB AXI4-Stream interface is a limited interface in that it does not allow throttling from the external connections. As a result, some of the standard AXI4-Stream signals are missing from the port list as well as the addition of the tuser signals. Both transmit and receive buses are 8-bits wide which eliminates the need of the write strobe signal bus. For both buses, the AXI Ethernet Subsystem provides the AXI4-Stream clocks and clock enables which are derived from the internal Ethernet clocks.

The AVB AXI4-Stream interface is connected to external logic that currently is not provided by AMD. Several third-party partners have created this logic, have tested it with the subsystem, and have integrated it into AVB systems. This external logic takes time-sensitive audio or video information and splits it into Ethernet frames using a protocol encoding that is similar to TCP/IP. This is performed in FPGA logic.

Ethernet AVB frames are passed back and forth to the Ethernet through the AVB AXI4-Stream interfaces. Internal to AXI Ethernet Subsystem, the AVB frames and the legacy frames are multiplexed and demultiplexed based on a prioritization and time slotting method. The AVB function in the AXI Ethernet Subsystem is responsible for helping to choose the most accurate AVB system clock in the Ethernet network and synchronizes to the clock so all AVB nodes are synchronized.