The AXI4-Lite signal ports are described in the following table.
| Signal Name | Direction | Description |
|---|---|---|
| s_axi_lite_clk | In | Clock. |
| s_axi_lite_resetn | In | Reset (active-Low). See Resets. |
| s_axi_awaddr[31:0] | In | Write address. |
| s_axi_awvalid | In | Write address valid: Indicates a valid write address and control information is available. |
| s_axi_awready | Out | Write address ready: Slave is ready to accept address and control information. |
| s_axi_wdata[31:0] | In | AXI write data bus. |
| s_axi_wstrb[3:0] | In | Write strobes: Indicates which byte lanes have valid data. s_axi_wstrb[n] corresponds to s_axi_wdata[(8xn)]+7:(8xn)] |
| s_axi_wvalid | In |
Write valid: Indicated valid write data and strobes are available.
|
| s_axi_wready | Out |
Write ready: Indicates the slave can accept the write data.
|
| s_axi_bresp[1:0] | Out | Write response: Indicates the status of the write transaction. |
| s_axi_bvalid | Out |
Write response valid: Indicates a valid write response is available.
|
| s_axi_bready | In |
Response ready: Indicates the master can accept the response information.
|
| s_axi_araddr[31:0] | In | Read address |
| s_axi_arvalid | In |
Read address valid: When High, this signal indicates the read address and control information is valid and remains valid until s_axi_arready is High.
|
| s_axi_arready | Out | Address ready: Indicates the slave is ready to accept an address and associated control signals. |
| s_axi_rdata[31:0] | Out | Read data. |
| s_axi_rresp[1:0] | Out | Read response: Indicates the status of the read transaction. |
| s_axi_rvalid | Out |
Read data valid: Indicates the read data is available and the read transfer can complete.
|
| s_axi_rready | In |
Read ready: Indicates the master can accept the read data and response information.
|