The Ethernet frame data to be transmitted and the frame data that is received passes between the AXI Ethernet Subsystem and the rest of the integrated system through AXI4-Stream interfaces. In many cases, the other end of the AXI4-Stream interfaces are connected to a soft IP DMA controller implemented in FPGA logic. However, any custom logic can be used to connect to the AXI4-Stream interface as long as it meets the requirements of the AXI Ethernet Subsystem AXI4-Stream interface.
The AXI4-Stream interface is a high-performance, synchronous, point-to-point connection which is described in Arm AMBA 4 AXI4-Stream Protocol v1.0 Specification (ARM IHI 0051A). This section describes the specific 32-bit implementation used by the AXI Ethernet Subsystem to transfer transmit and receive Ethernet frame data with the rest of the integrated system. The AXI4-Stream model used is called Packetized and Aligned Strobe, which is defined in the following sections.