Support for many PHY interfaces is included and is selected with parameters at build time. The PHY interface Table 3 supported does not vary based on the Ethernet MAC type selected. See the following table through for the supported PHY interface with TEMAC.
| TEMAC | |||
|---|---|---|---|
| 10 Mbps | 100 Mbps | 1000 Mbps | |
| PHY Interface | Full-Duplex | ||
| MII | Yes | Yes | No |
| GMI | Yes | Yes | Yes |
| RGMII v2.0 | Yes | Yes | Yes |
| SGMII | Yes | Yes | Yes |
| 1000BASE-X | No | No | Yes |
|
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For supported IO voltages in the following devices, refer to the documents mentioned below:
- UltraScale Architecture SelectIO Resources User Guide (UG571)
- Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Some of the optional functions provided by the AXI Ethernet Subsystem are not compatible with other optional functions. The following figure shows which of these functions are compatible with each other. In the following figure , TX/RX CSUM Offload refers to both Partial Checksum Offloading and Full Checksum Offloading.
The AXI Ethernet Subsystem provides one Ethernet interface. Access to external PHY registers is provided using a standard MII Management bus. When using the SGMII or 1000 BASE-X PHY interfaces, the AXI Ethernet Subsystem provides some PHY functionality and also includes PHY registers which are also accessible through the MII Management bus. These registers are described in Using the MII Management to Access Internal or External PHY Registers.
This subsystem includes optional logic to calculate TCP/UDP checksums for transmit and verify TCP/UDP checksums for receive. Using this logic can significantly increase the maximum Ethernet bus data rate while reducing utilization of the processor for Ethernet tasks. Including the checksum offload function increases the amount of FPGA resources used for this subsystem. The checksum information is included with each Ethernet frame passing over the AXI4-Stream interface. The checksum offload functionality cannot be used at the same time as the extended VLAN functionality.
The AXI Ethernet Subsystem provides memory buffering of transmit and receive Ethernet frames, thereby allowing more optimal transfer to and from the subsystem with DMA. The number of frames that can be buffered in each direction is based on the size of each frame and the size of the memory buffer which are selected by parameters at build time. If the AXI Ethernet Subsystem transmit memory buffer becomes full, it throttles the transmit AXI4-Stream Data interface until more room is available for Ethernet frames. If the receive memory buffer becomes full, frames are dropped until more memory buffer room is available. Receive frames that do not meet Ethernet format rules or do not satisfy receive address qualification are always dropped.
Optional logic can be included to facilitate handling of VLAN type frames. Auto insertion, stripping, or translation of VLAN frames can be performed on transmit or receive with several options for choosing which frames are to be altered. Additional logic can be selected to provide additional filtering of receive frames with multicast destination addresses. The AXI Ethernet Subsystem provides native support for up to four (4) multicast addresses.
Logic can be selected to gather statistics on transmit and receive frames. This logic provides 64-bit counters for many statistics about the frames passing through the TEMAC core. Ethernet AVB support is available with an additional license and is supported at 100 Mbps or 1000 Mbps implementations.