The example design of the AXI Ethernet Subsystem can be divided in to different components and hierarchies. The Support Level hierarchy contains elements that belong to the shared logic. The example design hierarchy is the top level for this HDL example design. HDL example design contains the following components:
- An instance of the AXI Ethernet Subsystem
- Clock management logic, including MMCM and Global Clock Buffer instances, where required
- MII, GMII, RGMII, SGMII, or 1000BASE-X interface logic, including IOB and DDR registers instances, where required
- User Transmit and Receive FIFOs with AXI4-Stream interfaces
- User basic pattern generator module containing a frame generator and a frame checker with loopback logic
- User AVB pattern generator module providing a second frame generator and checker for designs including the AVB endpoint
- A simple state machine to bring up the PHY (if any) and the Ethernet MAC to ready the design for frame transfer
The HDL example design provides basic loopback functionality on the user side of the AXI Ethernet Subsystem and connects the GMII/RGMII interface to external IOBs. The design also operates as a pattern generator with optional PHY-side external data loopback with automatic checking.
This configuration allows the functionality of the subsystem to be demonstrated either by using a simulation package as discussed in this guide, or directly in hardware when placed on a suitable board. The simple state machine assumes standard AMD demonstration board PHY address and register content.