When the Customize Block option is selected, a window appears showing different available configurations. These are organized in various tabs for better readability and configuration purposes.
The Board tab (available for non-AMD Versal™ Adaptive SoC only): The Board tab (see the following figure) is visible only when you select a non-Versal Adaptive SoC board in the current project. In this tab, options related to the board-based I/O constraints are provided. More details onboard support packages are available in the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).
- Generate Board based IO Constraints
- This option needs to be selected to make use of the board flow. If you do not
want to make use of board flow, this option can be left unchecked. If the tool
is able to generate the physical constraints for a given configuration, only
those options are active; otherwise, they are grayed out. When this option is
selected the following three interfaces can be enabled.
- Ethernet
- This option enables to select the type of Ethernet I/O interface available in board.
- MDIO
- This option enables to select the MDIO interface available in the board.
- DIFF_CLK
- This option allows you to select the serial transceiver clock source if that source is available on the board.
- PHYRST_N
- This option allows you to generate reset for an external PHY device. The minimum duration of this reset is 10ms at the maximum AXI4-Stream clock.
The Physical Interface tab: This tab is related to the physical interfaces that are available. The following options are available in this tab:
- Ethernet Speed
- Supported types are 1 Gbps and 2.5 Gbps.
- Physical Interface Selection
- The physical interface type is selected using this option. The PHY types supported are MII, GMII, RGMII, SGMII, 1000BASE-X, and both.
- SGMII LVDS Option
- The LVDS mode is enabled only in the SGMII or 1000BASE-X mode of operation.
- MDIO PHY Address
- PHY address is the address for the MDIO interface for the Gigabit Ethernet PCS PMA PHY address. The PHY address can be set using this option.
- GT Reference Clock Frequency MHz
- This is the reference clock input to GT. The valid values are 125 MHz, 156.25 MHz, 250 MHz, and 312.5 MHz. For Versal devices, 500MHz and 625 MHz reference clock input is supported in addition to the above list.
- Enable Transceiver Control Debug Interface
- If selected, enables addition transceiver control ports for TX Driver, RX Equalization and other features such as PRBS. This is available only in non LVDS mode in SGMII or 1000BASE-X modes.
The MAC Features tab: The MAC Features tab has options related to the Ethernet MAC functionality. The following options are available in this tab:
- Enable Processor Features: In processor mode, the axi_ethernet_buffer is present and driver support is available. Processor mode can be disabled only when PHY_TYPE is 1000BASE-X or SGMII. For 7 series devices, there is no processor mode support for the 2.5G data rate.
- Processor Mode Options
- TX and RX memory sizes can be selected using the TX Memory Size and RX Memory Size options.
- TX and RX checksum offload capability can be selected using the RX Checksum Offload and TX Checksum Offload options.
- RX extended multicast filtering can be enabled with the Enable RX extended multicast address filtering option.
- Advanced VLAN options for TX and RX data streams for VLAN tagging, VLAN stripping, and VLAN translation are selected using the respective options.
- Flow Control Options: Enables priority-based flow control options. This can be enabled only when processor_mode is deselected.
- Statistics Counter Options: Use this option to enable the statistic counters. Enable Statistics Counters should be selected for this purpose. By selecting the Allow Statistics to be reset option, the statistics reset capability can be enabled. The width of the statistics counter can be selected using the Statistics Counter Width option.
- Frame Filter Options: Enables the TEMAC filters.
The Network Timing tab: The 1588 options are enabled only when PHY_TYPE is 1000BASE-X or SGMII in 1G and 2.5G modes of operation and not in LVDS mode. This tab is used to configure the 1588 and AVB modes. The following options are available in this tab:
-
Enable 1588: This enables the 1588 mode of
operation. The following sub-options are enabled only when Enable 1588 is enabled.
TCP/UDP hardware checksum offload is not supported/calculated
when the 1588 feature is enabled.
- 1-step or 2-step Support: This enables the 1-step or 2-step operation method of 1588. This is enabled only when Enable 1588 is selected.
- Selection of the Time-of-Day (ToD) timer and timestamp format or the Correction Field Format timer and timestamp format.
- 1588 System Timer reference clock period in ps : This is the 1588 system reference clock period in picoseconds.
- Enable AVB: This enables Audio Video Bridging functions. This can be enabled only when 1588 mode is disabled.
The Shared Logic tab (available for non-Versal Adaptive SoC only): The Shared Logic tab (See the following figure) selects whether shared logic is included in the subsystem. Shared logic is different for different configurations. In GMII mode IDELAYCTRL is the shared element. In RGMII mode, IDELAYCTRL and the TX MMCM with its associated clock buffers for AMD Artix™ 7 or AMD Kintex™ 7 devices are shared logic. There is no shareable logic in MII mode. In SGMII using transceiver mode or 1000BASE-X Mode, the transceiver differential reference clock buffer, mixed mode clock manager (MMCM), and clock buffer are shared elements. In SGMII over LVDS, the transceiver differential reference clock buffer, MMCM, IDELAYCTRL and clock buffer are shared elements. The options for Shared Logic select whether to include or not include shared logic in the subsystem.
GT in Example Design: This option is available only when you select Include Shared Logic in IP Example Design option (available for non-Versal Adaptive SoC only). This moves the transceiver from the core to the Support level instance. When this option is selected, generation of additional transceiver control and status ports is disabled. This option is available only for AMD UltraScale™ and AMD UltraScale+™ architecture designs.
The OOC Settings tab: In OOC mode, these clock frequency values are used by the synthesis tool.
The Locations tab: This tab is available for UltraScale and UltraScale+ devices in SGMII and 1000BASE-X modes. In non-LVDS mode the gt xy coordinates can be selected. In Asynchronous 1000BASE-X/SGMII over LVDS mode the bit slice locations need to be selected. Refer to the “Layout and Placement” section of the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).
