To allow you to generate an AXI Ethernet Subsystem that is uniquely tailored to your design, These parameters can be configured through the Vivado IDE. In addition to the parameters listed in the following table, embedded development kit (EDK) tools infer a few other parameters. These parameters control the behavior of the software generated. All parameters inferred by the EDK tools are listed in the following table.
| Parameter | Default Value | Description |
|---|---|---|
| USE_BOARD_FLOW | FALSE | If TRUE, this enables generation of Board based I/O Constraints. If you select a board in the Project settings, the default value will be TRUE. |
| PHY_TYPE | GMII | Select the PHY Interface type |
| Enable_1588 | FALSE | Enables 1588 timestamping support. This parameter is enabled only when PHY_TYPE is set to 1000BASE-X or SGMII and not in LVDS mode. |
| Enable_1588_firstep | TRUE |
TRUE: 1-step support FALSE: 2-step support |
| TIMER_CLK_PERIOD | 4000 | 1588 System Timer reference clock period in picoseconds |
| SupportLevel | 1 | This verifies if the Shared Logic is in the subsystem or not. Default value is to include shared logic in the subsystem. If Support Level is 1, it specifies Include Shared Logic in Core. If SupportLevel is 0, it specifies Include Shared Logic in IP Example Design. |
| ENABLE_LVDS | FALSE | Enable standard I/O (LVDS) for SGMII or 1000BASEX |
| ENABLE_AVB | FALSE | Enable AVB |
| TXVLAN_TRAN | FALSE | Enable TX VLAN translation |
| RXVLAN_TRAN | FALSE | Enable RX VLAN translation |
| TXVLAN_TAG | FALSE | Enable TX VLAN tagging |
| RXVLAN_TAG | FALSE | Enable RX VLAN tagging |
| TXVLAN_STRP | FALSE | Enable TX VLAN stripping |
| RXVLAN_STRP | FALSE | Enable RX VLAN stripping |
| MCAST_EXTEND | FALSE | Enable RX extended multicast address filtering |
| Frame_Filter | FALSE | Frame Filter |
| Statistics_Reset | FALSE | Allow Statistics to be reset |
| Statistics_Counters | FALSE | Enable statistics counters |
| Number_of_Table_Entries | 4 | Number of Table Entries |
| PHYADDR | 1 1 | MDIO PHY Address, range 1 to 31 |
| Statistics_Width | 64 bit | Statistics Counter Width |
| RXMEM | 4k | RX Memory Size |
| TXMEM | 4k | TX Memory Size |
| TXCSUM | FALSE | TX Checksum Offload |
| RXCSUM | FALSE | RX Checksum Offload |
| SIMULATION_MODE | 0 | Enable Simulation Mode helps reducing the simulation time. |
| Include_IO | TRUE |
Include the I/O elements. If this is TRUE, I/O elements are included. If this is FALSE, I/O elements are not included in the subsystem. This is available only in GMII mode. When this is FALSE, TEMAC is configured in internal mode. |
| processor_mode | TRUE |
When TRUE, buffer module is included and drivers are available. When FALSE, the buffer module is not available and the drivers are not present. This parameter can only be updated when PHY_TYPE is SGMII or 1000BASE-X. |
| TransceiverControl | FALSE |
This enables the debug interface when a transceiver is instantiated in the AXI 1G/2.5G Ethernet subsystem. When the transceiver debug interface is enabled, the drp clock input port is available at the top level and its frequency is programmable. When the transceiver debug port is disabled, the drp clock port of the transceiver is not available at the top level. It is internally connected to reference clock port and its frequency is fixed. |
| Enable_Pfc | FALSE | This enables the support for the Priority Flow Control. |
| speed_1_2p5 | 1G |
This sets the data rate to 1G or 2.5G.
|
| drpclkrate | 50.0 | This is the frequency (in MHz) connected to the drp_clk. This is enabled only when TransceiverControl parameter is enabled. In AMD UltraScale™ devices when TransceiverControl is disabled, this value is fixed at 50.0 MHz. |
| gtrefclkrate | 125 | This is the frequency (in MHz) of the GT reference clock. Valid values are selected through Vivado IDE. This is applicable only for UltraScale devices. |
| lvdsclkrate | 125 | This is the frequency (in MHz) of the LVDS reference clock. Valid values are selected through Vivado IDE. This is applicable only for UltraScale devices. |
| gt_type | GTH | This selects the GT type when the project part supports multiple GT types. Valid Values are selected through Vivado IDE. |
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