Ethernet MII Interface - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The Ethernet MII ports are described in the following table.

Table 1. Ethernet MII Ports
Signal Name Direction Description
mii_txd[3:0] Out TEMAC to PHY transmit data. Initial status 0.
mii_tx_en Out TEMAC to PHY transmit enable. Initial status 0.
mii_tx_er Out TEMAC to PHY transmit Error enable. Initial status 0.
mii_rxd[3:0] In PHY to TEMAC receive data.
mii_rx_dv In PHY to TEMAC receive data valid indicator.
mii_rx_er In PHY to TEMAC receive error indicator.
mii_rx_clk In PHY to TEMAC receive clock.
mii_tx_clk In PHY to TEMAC transmit clock (also used for GMII/MII mode). See Clocking.