Ethernet System Interface - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The Ethernet system ports are described in the following table.

Table 1. Ethernet System Ports
Signal Name Direction Description
phy_rst_n Out PHY reset signal: This active-Low reset is held active for 10 ms after power is applied and during any reset. After the reset goes inactive, the PHY cannot be accessed for an additional 5 ms. Initial status 0.
ref_clk In

This is a stable global clock used by signal delay primitives and transceivers in those respective modes.

The clock frequency is 200 MHz for 7 series FPGAs.

For UltraScale/UltraScale+/Versalarchitecture, the frequency range is 300-1333 MHz for GMII and RGMII modes. For detailed information, see the Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051).

When a PCS PMA core exists, it drives the independent clock of 1000BASE-X PCS/PMA. The clock frequency is 50 MHz for UltraScale/UltraScale+/Versal Adaptive SoC. For detailed information on the clock requirements, see the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).

gtx_clk In The 125 MHz clock used in all GMII, RGMII, and SGMII configurations to control the PHY reset requirements. Also, it is a 125 MHz input clock on global clock routing used to derive the other transmit clocks for all GMII and RGMII PHY modes. This clock is also used when Ethernet Statistics are enabled with all supported device families. See Clocking.
mgt_clk_p In Positive polarity of differential clock used to drive GT serial transceivers. Must be connected to an external, high-quality differential reference clock of frequency of 125 MHz.
mgt_clk_n In Negative polarity of differential clock used to drive GT serial transceivers. Must be connected to an external, high-quality differential reference clock of frequency of 125 MHz.
signal_detect In This signal should be routed to an appropriate port on the optical SFP module. It is required to detect cable pull conditions cleanly. If not used, it needs to be tied up to 1.
clk_en In This signal is present only in GMII mode and when the include_io option is deselected. In 10/100 MHz mode, this needs to be connected to the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP clock_en output port, else tie to 1.