When multiple subsystem instances are targeted for transceivers in the same quad, the GTCOMMON and IBUFDS need to be shared. The transceiver outputs of the instance configured to Include Shared Logic in Core need to be connected to inputs of an instance configured to Include Shared Logic in IP Example Design . An example where the RX clock is synchronous between both the instances is shown in the following figure. The connections shown in blue are specific to connections for sharing logic. The rest are regular connections.
For shared logic connectivity guidelines, see Table 3-1 in the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).
For Clock Management with Multiple Core Instances for SGMII, see the “Clock Sharing Across Multiple Cores with Transceivers and FPGA Logic Elastic Buffer” section in 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).