When multiple subsystem instances are targeted for LVDS ports using Asynchronous 1000BaseX/SGMII over LVDS in the same bank, the clocking resources and reset sequence can be shared. The signals to/from instance configured to Include Shared Logic in Core needs to be connected to inputs of an instance configured to Include Shared Logic in IP Example Design. For Versal devices, XPLL is always included in the core and RIU reset state machine is included in example design. This is described in detail in the "Asynchronous 1000BASE-X/SGMII over LVDS" section in the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).