Example Design - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

This chapter contains information about the example design provided in the AMD Vivado™ Design Suite. This example design is intended to directly target the key AMD demonstration families under certain core configurations. The current example design targets the AMD Kintex™ 7 FPGA KC705 Evaluation Kit board. Information about targeting the example design to the Kintex AMD UltraScale™ KCU105 board is also provided in this chapter.

The example design includes a basic state machine that uses the AXI4-Lite interface to bring up the external PHY and Ethernet MAC allowing basic frame transfers. A simple frame generator and frame checker are also included to provide a packet generator with optional checking of any received data. If the AXI Ethernet Subsystem is generated with the optional AVB endpoint, another frame generator and frame checker are included to exercise the additional AV datapath.

Loopback functionality is provided as either MAC RX to TX (loopback logic replaces the packet generator as the packet source), or PHY TX to RX (loopback logic replaces the demonstration test bench stimulus and checker). Push buttons and DIP switches on the board provide basic control of the state machine allowing Ethernet MAC bit rate change. See the board-specific sections in Targeting the Example Design to a Board. The following figure illustrates the top-level of the AXI Ethernet Subsystem HDL example design.

Figure 1. HDL Example Design AXI Ethernet Page-1 Rectangle 8pt. Arial Text System Clocks and Resets System Clocksand Resets 8pt. Arial Text.3 DIP Switches Push Buttons DIP SwitchesPush Buttons 8pt. Arial Text.4 Example Design Example Design Rectangle.5 Example Design Clocks and Reset Generator Example Design Clocksand Reset Generator Rectangle.6 AXI4-Lite Control State Machine AXI4-Lite ControlState Machine Large Arrow Large Arrow.8 Rectangle.9 8pt. Arial Text.10 AXI4-Stream Pattern Generator and Checker AXI4-Stream PatternGenerator and Checker Rectangle.11 TX and RX FIFO TX and RX FIFO Rectangle.12 Slave Loopback Slave Loopback Rectangle.13 Pattern Generator and Checker Pattern Generatorand Checker Rectangle.14 AVB Pattern Generator and Checker AVB Pattern Generatorand Checker Rectangle.15 8pt. Arial Text.16 Support Level Support Level Rectangle.17 Support Level Clocks and Reset Generator Support Level Clocksand Reset Generator Large Arrow.18 Rectangle.19 Support Level IDelay Control Support Level IDelayControl Rectangle.20 Support Level Transceiver Common Support Level Transceiver Common Large Arrow.21 Large Arrow.22 8pt. Arial Text.23 AXI Ethernet Subsystem AXI Ethernet Subsystem Rectangle.24 Large Arrow.25 Large Arrow.26 Large Arrow.27 Large Arrow.28 Large Arrow.29 Large Arrow.30 8pt. Arial Text.31 PHY Side Connections MII/GMII/RGMII/ SGMII/ 1000BaseX PHY SideConnectionsMII/GMII/RGMII/SGMII/1000BaseX 8pt. Arial Text.32 MDIO Interface MDIOInterface Large Arrow.33 Large Arrow.34 Large Arrow.35 Sheet.36 Sheet.37 8pt. Arial Text.38 Activity Indicator, LED Connections Activity Indicator, LED Connections Sheet.39 X18673-043019 X18673-043019