Gigabit Ethernet PCS/PMA Management Registers

The Gigabit Ethernet PCS PMA core has configuration registers as defined in IEEE 802.3. These have an address range from 0 to 15. These registers are configured using the MDIO interface. These registers are provided here for quick reference. For more information about these registers see the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).

These registers contain information relating to the operation of the 1000BASE-X PCS/PMA sublayer, including the status of the physical Ethernet link (PHY Link). Additionally, these registers are directly involved in the operation of the 1000BASE-X auto-negotiation function which occurs between the subsystem and its link partner, the Ethernet device connected at the far end of the PHY Link. These registers are accessed through the MII Management interface (Using the Address Filters). These registers are only valid when using the 1000BASE-X PHY interface.

Table 1. Gigabit Ethernet PCS PMA Internal Management Registers
Register Name	Register Address (REGAD)
Control register	0
Status register	1
PHY Identifier	2,3
Auto-Negotiation Advertisement register	4
Auto-Negotiation Link Partner Ability Base register	5
Auto-Negotiation Expansion register	6
Auto-Negotiation Next Page Transmit register	7
Auto-Negotiation Next Page Receive register	8
Extended Status register	15
Vendor Specific register: Auto-Negotiation Interrupt Control register	16
Vendor Specific register: Loopback Control register	17

Table 2. Control Register (Register 0)
Bits	Name	Access	Reset Value	Description
15	Reset	R/W Self clearing	0	1 = Subsystem Reset 0 = Normal Operation
14	Loopback	R/W	0	1 = Enable Loopback Mode 0 = Disable Loopback Mode When used with a device-specific transceiver, the subsystem is placed in internal loopback mode. With the TBI version, Bit 1 is connected to ewrap. When set to 1, indicates to the external PMA module to enter loopback mode.
13	Speed Selection (LSB)	Returns 0	0	Always returns a 0 for this bit. Together with bit 0.6, speed selection of 1000 Mbps is identified
12	Auto-Negotiation Enable	R/W	1	1 = Enable Auto-Negotiation Process 0 = Disable Auto-Negotiation Process
11	Power Down	R/W	0	1 = Power down 0 = Normal operation With the PMA option, when set to 1 the device-specific transceiver is placed in a low-power state. This bit requires a reset (see bit 0.15) to clear. With the TBI version this register bit has no effect.
10	Isolate¹	R/W	1	1 = Electrically Isolate PHY from GMII 0 = Normal operation
9	Restart Auto-Negotiation	R/W Self clearing	0	1 = Restart Auto-Negotiation Process 0 = Normal Operation
8	Duplex Mode	Returns 1	1	Always returns a 1 for this bit to signal Full-Duplex Mode.
7	Collision Test	Returns 0	0	Always returns a 0 for this bit to disable COL test.
6	Speed Selection (MSB)	Returns 1	1	Always returns a 1 for this bit. Together with bit 0.13, speed selection of 1000 Mbps is identified.
5	Unidirectional Enable	R/W	0	Enable transmit regardless of whether a valid link has been established. This feature is only possible if Auto-Negotiation Enable bit 0.12 is disabled.
4:0	Reserved	Returns 0s	00000	Always return 0s, writes ignored.
When using the 1000BASE-X TEMAC core (C_TYPE = 1 and C_PHY_TYPE = 5), set the isolate bit to zero (Control register 0 bit 10). The subsystem is not operational until this is completed.

The following table shows the Gigabit Ethernet PCS PMA Management Status register bit definitions.

Table 3. Management Status Register (Register 1)
Bits	Name	Access	Reset Value	Description
15	100BASE-T4	Returns 0	0	Always returns a 0 for this bit because 100BASE-T4 is not supported.
14	100BASE-X Full Duplex	Returns 0	0	Always returns a 0 for this bit because 100BASE-X full-duplex is not supported.
13	100BASE-X Half Duplex	Returns 0	0	Always returns a 0 for this bit because 100BASE-X half-duplex is not supported.
12	10 Mbps Full Duplex	Returns 0	0	Always returns a 0 for this bit because 10 Mbps full-duplex is not supported.
11	10 Mbps Half Duplex	Returns 0	0	Always returns a 0 for this bit because 10 Mbps half-duplex is not supported.
10	100BASE-T2 Full Duplex	Returns 0	0	Always returns a 0 for this bit because 100BASE-T2 full-duplex is not supported.
9	100BASE-T2 Half Duplex	Returns 0	0	Always returns a 0 for this bit because 100BASE-T2 half-duplex is not supported.
8	Extended Status	Returns 1	1	Always returns a 1 for this bit indicating the presence of the extended register (register 15).
7	Unidirectional Ability	Returns 1	1	Always returns a 1.
6	MF Preamble Suppression	Returns 1	1	Always returns a 1 for this bit to indicate the support of management frame preamble suppression.
5	Auto-Negotiation Complete	RO	0	0 – auto-negotiation process not completed 1 – auto-negotiation process complete
4	Remote Fault	RO self clearing on read	0	0 – no remote fault condition detected 1 – remote fault condition detected
3	Auto-Negotiation Ability	Returns 1	1	Always returns a 1 for this bit indicating that the PHY is capable of auto-negotiation.
2	Link Status	RO self clearing on read	0	0 – PHY Link is down 1 – PHY Link is up
1	Jabber Detect	Returns 0	0	Always returns a 0 for this bit because no jabber detect is supported.
0	Extended Capability	Returns 0	0	Always returns a 0 for this bit because no extended register set is supported.

The following table shows the first Management PHY Identifier register bit definitions.

Table 4. Management PHY Identifier (Register 2)
Bits	Name	Access	Reset Value	Description
15:0	OUI	RO	0x0000	Organizationally Unique Identifier (OUI).

The following table shows the second Management PHY Identifier register bit definitions.

Table 5. Management PHY Identifier (Register 3)
Bits	Name	Access	Reset Value	Description
15:10	OUI	RO	000000	Organizationally Unique Identifier (OUI).
9:4	MMN	Returns 0	000000	Manufacturer Model Number. Always returns 0s.
3:0	Revision	Returns 0	0000	Revision Number. Always returns 0s.

The following table shows the Management Auto-Negotiation Advertisement register bit definitions.

Table 6. Management Auto-Negotiation Advertisement Register (Register 4)
Bits	Name	Access	Reset Value	Description
15	Next Page	R/W	0	0 – next page functionality is not advertised 1 – next page functionality is advertised
14	Reserved	Returns 0s	0	Always return zeros.
13:12	Remote Fault	R/W self clearing after auto-negotiation	0x0	00 – no error 01 – off line 10 – link failure 11 – auto-negotiation error
11:9	Reserved	Returns 0s	0x0	Always return zeros.
8:7	Pause	R/W	0x3	00 – No pause 01 – Symmetric pause 10 – Asymmetric pause towards link partner 11 – both symmetric pause and asymmetric pause towards link partner
6	Half Duplex	Returns 0s	0	Always return zeros because half-duplex is not supported.
5	Full Duplex	R/W	1	0 – full-duplex mode is not advertised 1 – full-duplex mode is advertised
4:0	Reserved	Returns 0s	0x0	Always return zeros.

The following table shows the TEMAC Internal 1000BASE-X PCS/PMA Management Auto-Negotiation Link Partner Ability Base register bit definitions.

Table 7. Management Auto-Negotiation Link Partner Ability Base Register (Register 5)
Bits	Name	Access	Reset Value	Description
15	Next Page	RO	0	0 – next page functionality is not supported 1 – next page functionality is supported
14	Acknowledge	RO	0	Used by the auto-negotiation function to indicate reception of a link partner base or next page.
13:12	Remote Fault	RO	0x0	00 – no error 01 – offline 10 – link failure 11 – auto-negotiation error
11:9	Reserved	Returns 0s	0x0	Always return zeros.
8:7	Pause	RO	0x	00 – no pause 01 – asymmetric pause supported 10 – symmetric pause supported 11 – both symmetric pause and asymmetric pause supported
6	Half Duplex	RO	0	0 – half-duplex mode is not supported 1 – half-duplex mode is supported
5	Full Duplex	RO	0	0 – full-duplex mode is not supported 1 – full-duplex mode is supported
4:0	Reserved	Returns 0s	0x0	Always return zeros.

The following table shows the Management Auto-Negotiation Expansion register bit defiitions.

Table 8. Management Auto-Negotiation Expansion Register (Register 6)
Bits	Name	Access	Reset Value	Description
15:3	Reserved	Returns 0s	0x0	Always return zeros.
2	Next Page Able	Returns 1	1	Always returns a 1 for this bit because the device is Next Page Able.
1	Page Received	RO self clearing on read	0	0 – a new page is not received 1 – a new page is received
0	Reserved	Returns 0s	0	Always return zeros.

The following table shows the Management Auto-Negotiation Next Page Transmit register bit definitions.

Table 9. Management Auto-Negotiation Next Page Transmit Register (Register 7)
Bits	Name	Access	Reset Value	Description
15	Next Page	R/W	0	0 – last page 1 – additional next pages to follow
14	Reserved	Returns 0s	0	Always return zeros.
13	Message Page	R/W	1	0 – unformatted page 1 – message page
12	Acknowledge 2	R/W	0	0 – cannot comply with message 1 – complies with message
11	Toggle	RO	0	Value toggles between subsequent pages.
10:0	Message or unformatted Code Field	R/W	0x001 (null message code)	Message code field or unformatted page encoding as dictated by bit 13.

The following table shows the Management Auto-Negotiation Next Page Receive register bit definitions.

Table 10. Management Auto-Negotiation Next Page Receive Register (Register 8)
Bits	Name	Access	Reset Value	Description
15	Next Page	RO	0	0 – last page 1 – additional next pages to follow
14	Acknowledge	RO	0	Used by auto-negotiation function to indicate reception of a link partner base or next page.
13	Message Page	RO	0	0 – unformatted page 1 – message page
12	Acknowledge 2	RO	0	0 – cannot comply with message 1 – complies with message
11	Toggle	RO	0	Value toggles between subsequent pages.
10:0	Message or unformatted Code Field	RO	0x0 (null message code)	Message code field or unformatted page encoding as dictated by bit 13.

The following table shows the Management Extended Status register bit definitions.

Table 11. Management Extended Status Register (Register 15)
Bits	Name	Access	Reset Value	Description
15	1000BASE-X Full Duplex	Returns 1	1	Always returns a 1 for this bit because 1000BASE-X full-duplex is supported.
14	1000BASE-X Half Duplex	Returns 0	0	Always returns a 1 for this bit because 1000BASE-X half-duplex is not supported.
13	1000BASE-T Full Duplex	Returns 0	0	Always returns a 1 for this bit because 1000BASE-T full-duplex is not supported.
12	1000BASE-T Half Duplex	Returns 0	0	Always returns a 1 for this bit because 1000BASE-T half-duplex is not supported.
11:0	Reserved	Returns 0s	0x0	Always return zeros.

The following table shows the Management Auto-Negotiation Interrupt Control register bit definitions.

Table 12. Management Auto-Negotiation Interrupt Control Register (Register 16)
Bits	Name	Access	Reset Value	Description
15:2	Reserved	Returns 0s	0	Always return zeros.
1	Interrupt Status	R/W	0	If the interrupt is enabled, this bit is asserted upon the completion of an auto-negotiation cycle; it is only cleared by writing 0 to this bit. If the interrupt is disabled, this bit is set to 0. This is the auto-negotiation complete interrupt. 0 – interrupt is asserted 1 – interrupt is not asserted
0	Interrupt Enable	R/W	1	0 – interrupt is disabled 1 – interrupt is enabled

Table 13. Management Loopback Control Register (Register 17)
Bits	Name	Access	Reset Value	Description
15:1	Reserved	Returns 0s	0	Always return zeros.
0	Loopback Position	R/W	0	Loopback is enabled or disabled using register 0 bit 14. 0 – loopback (when enabled) occurs directly before the interface to the GTX transceiver 1 – loopback (when enabled) occurs in the GTX transceiver

Gigabit Ethernet PCS/PMA Management Registers - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)