Hardware Debug - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English
Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The Vivado Design Suite debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the Vivado Design Suite debug feature for debugging the specific problems.

Ensure that all the timing constraints for the subsystem were properly incorporated from the example design and that all constraints were met during implementation. Following is a list of some general checks.

  • Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
  • If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
  • If your outputs go to 0, check your licensing.
  • Different PHYs have different reset polarity. Check the reset polarity.