IEEE 1588 System Timer Ports - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID: PG138
Release Date: 2023-11-15
Version: 7.2 English

The 1588 system-wide Time-of-Day (ToD) timer are provided to the subsystem using the ports defined in the following table.

Table 1. IEEE 1588 System Timer Ports
Name	Clock Domain	Description
systemtimer_clk¹	–	System reference clock for the system timer provided to the subsystem.
systemtimer_s_field[47:0]	systemtimer_clk	The 48-bit seconds field of the 1588-2008 system timer. This increments by 1 every time the systemtimer_ns_field is reset back to zero.
systemtimer_ns_field[31:0]	systemtimer_clk	The 32-bit nanoseconds field of the 1588-2008 system timer. This counts from 0 up to (1x10^9)-1 [1 second], and then resets back to zero.
If the system is using sync-E and the recovered clock is used to drive the systemtimer_clk, the frequency could be in multiples of userclk. For any other systems, AMD recommends that rising edges of the systemtimer_clk clock be close to rising edges of usrclk so that accurate value can be sampled on the userclk domain. This can be achieved by having the systemtimer_clk running at a much higher frequency as compared to usrclk.

Table 2. 1588 Correction Field Ports
Name	Clock Domain	Description
systemtimer_clk¹	–	Clock for the system timer provided to the subsystem.
correction_timer[63:0]	systemtimer_clk	Bits [63:16] represent a 48-bit ns field. Bits[15:0] represents a fractional ns field. Bit 15 represents a half ns. Bit 14 represents a quarter ns. Bit 13 represents one-eighth ns, etc.
If the system is using sync-E and the recovered clock is used to drive the systemtimer_clk, the frequency could be in multiples of userclk. For any other systems, AMD recommends that rising edges of the systemtimer_clk clock be close to rising edges of usrclk so that accurate value can be sampled on the userclk domain. This can be achieved by having the systemtimer_clk running at a much higher frequency as compared to usrclk.