|
Subsystem Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive SoC, AMD UltraScale+™
, AMD Kintex™
UltraScale™
, AMD Virtex™
UltraScale™
, AMD Zynq™ 7000 SoC, 7 series
FPGAs |
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream
|
| Resources |
Performance and Resource Utilization
|
| Provided with
Subsystem
|
| Design Files |
Encrypted register transfer level (RTL) |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Not Provided |
| Simulation Model |
Verilog and VHDL source HDL Model |
| Supported S/W Driver
2
|
Standalone and Linux |
| Tested Design
Flows
3
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 54668
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs:
72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
-
Standalone driver details can be found on the AXI Ethernet Standalone Driver page.
Linux driver support information is available from the AXI Ethernet Linux Driver page.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|