The KCU105 board supports only SGMII over LVDS to connect
to the on-board PHY. In this mode, the MGT CLOCK is provided by the on-board PHY at 625 MHz
only. Also, the on-board PHY receives the reset from the FPGA. Because the AXI Ethernet
Subsystem generates phy_reset_n on the GTX clock, there might be a deadlock
in the reset state. To avoid this, the example design needs to be modified to disconnect the
phy_reset_n generated by the AXI Ethernet Subsystem and connect another
active-Low reset. This can be done in the example design wrapper. The required number of LEDs,
DIP switches, and push button switches are same as that are required for the KC705 board. The
required location constraints need to be added.