Logic Utilization - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID

PG138

Release Date

2023-11-15

Version

7.2 English

The following table shows the logic utilization for the IEEE 1588 hardware timestamping solutions, inclusive of the TEMAC and 1000BASE-X cores. These numbers do not include the Statistic Counters option.

Table 1. Logic Utilization for the IEEE 1588 Hardware Timestamping Solutions
Option	LUT as logic	LUT as Distributed RAM	LUT as Shift Register	Register as Flip-flop	Register as Latch	RAMB36	RAMB18	DSPs	MMCMs	BUFGs
1-Step and 2-Step support	2630	330	50	3840	0	0	0	0	1	2
2-Step only support	2300	330	150	3340	0	0	0	0	1	2