The AXI Ethernet Subsystem can be added to the canvas in the AMD Vivado™ IP integrator block design. The subsystem can also be used in a register transfer level (RTL) flow when selected from the IP catalog in the Vivado Integrated Design Environment (IDE). The catalog allows customization, instantiation within a design, output product generation, behavioral simulation, design elaboration, synthesis and implementation, and bitstream generation for the target device. The AXI Ethernet Subsystem represents a hierarchical design block containing multiple infrastructure cores that are configured and connected during the system design session. Each of the infrastructure cores can also be added directly to a block design (outside of the AXI Ethernet Subsystem).
This subsystem provides additional functionality and ease of use related to Ethernet. Based on the configuration, this subsystem creates interface ports, instantiates required infrastructure cores, and connects these cores. Infrastructure cores for this subsystem are the AMD Tri-Mode Ethernet MAC (TEMAC) and 1G/2.5G Ethernet PCS/PMA or Serial Gigabit Media Independent Interface (SGMII) cores. Additional functionality is provided using the AXI Ethernet Buffer core.
For detailed specifications, see Product Specification. See the change log for this subsystem for the core versions used with this design. All core documents can be downloaded from Xilinx.com.