The receive interface provides an AXI4-Stream
clock and which is derived from the TEMAC receive client interface and uses the
axi_str_avbrx_tvalid signal as a clock enable derived from the receive
client interface clock enable. These signals behave similarly to the transmit interface when
the Ethernet bus speed changes.
When the AXI Ethernet Subsystem has received an AVB frame
to transfer over the AXI4-Stream to the external logic, it drives the
axi_str_avbrx_tvalid signal High and provides a new
axi_str_avbrx_tdata byte value on each clock cycle when
axi_str_avbrx_tvalid signal is High. The destination cannot throttle and
must always be ready to receive a frame. After the AXI Ethernet Subsystem transfers the second
to last byte, it drives the axi_str_avbrx_tvalid signal Low and wait until it
gets a good or bad frame indication from the TEMAC before it finishes the frame. When it
receives the good or bad frame indication, it drives the axi_str_avbrx_tvalid
signal High again for one clock/ axi_str_avbrx_tvalid cycle along with the
last byte value. It drives the axi_str_avbrx_tuser signal High if the frame
is bad. If the frame is good, it drives axi_str_avbrx_tuser signal Low while
driving the axi_str_avbrx_tlast signal High.
All receive frames, good or bad, that meet the address
filtering rules, appear on the receive AXI_STREAM interface with the only indication of good
versus bad being the value of axi_str_avbrx_tuser during
axi_str_avbrx_tlast. The following figure shows the receive waveforms for
the AVB interface operating at 100 Mbps.
