Receiver Latency and Timestamp Adjustment - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The previous figure illustrates a block called Timer Sample and subtract known RX PHY latency . This illustrates the timestamp point in the receiver pipeline when the SFD is observed. This timestamp is performed in the 1000BASE-X PHY block, prior to any variable length latency logic.

  • The 7 series FPGA GTX transceiver provides a fixed and deterministic latency through its receiver path. This is achieved by using the GTX transceiver in RX buffer Bypass mode.
  • The 1000BASE-X core provides a fixed latency for the receiver path up until the timestamp point.

The logic is also then capable of adjusting the ToD timestamp value taken by subtracting a configurable duration (see bit 22 of Table 1). This value is user adjustable, but its default is initialized with the receiver path latency (transceiver and 1000BASE-X logic) prior to the timestamping position. This results in the returned timestamp value representing the time at which the Start codegroup appeared on the transceiver serial input. This latency adjust functionality can be applied to either of the ToD or Correction Field formats. The Correction Field value is provided to the subsystem in “1588 Correction Field Mode” using a 64-bits port. This Correction Field value is in a numerical format as defined in IEEE 1588 clause 13.3.2.7. These details are provided in Table 2.