Receiving a Pause Control Frame - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

When an error free frame is received by the subsystem, it examines the following information:

  • The destination address field is compared to the pause control address and the configured unicast address.
  • The Length/Type field is compared against the control type code (0x8808).
  • The opcode field contents are matched against the pause control opcode (0x0001).

If compare step 2 or 3 fails, or if flow control for the receiver is disabled (FCC register bit 29 is 0, see the Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051), the frame is ignored by the flow control logic and is passed to you. If the frames pass all three compare steps and receive flow control is enabled, the pause parameter in the frame is used to inhibit transmitter operation for the time defined in the IEEE Std 802.3-2008 specification.

A Receive Reject interrupt is activated (see bit 28 in Interrupt Status Register), and the frame is not passed up to software. If the transmitter is paused and a second pause frame is received, the current pause value of the transmitter is replaced with the new pause value received, including a possible value of 0x0.